On 12/10/2013 09:58 AM, Tom Musta wrote:
>> > The second test can never be true, since ra has 32 zero bits.
>> > Thus the first test is also pointless.
> Hmm. Consider the case where GPR[RA] = 0x_8000 (U=don't care) and
> GPR[RB] = 0x_. Without these checks, I do not b
On 12/9/2013 6:26 PM, Richard Henderson wrote:
>> +tcg_gen_shli_i64(ra, cpu_gpr[rA(ctx->opcode)], 32);
>> \
>> +/* check for MIN div -1 */
>> \
>> +int l3 = gen_new_label();
On 12/09/2013 07:47 AM, Tom Musta wrote:
> +/* does the result fit in 32 bits? */
> \
> +tcg_gen_brcondi_i64(TCG_COND_LT, cpu_gpr[rD(ctx->opcode)],
> INT32_MIN, \
> +lbl_ov);
> \
This patch addes the Signed and Unsigned Divide Word Extended
instructions which were introduced in Power ISA 2.06.
Signed-off-by: Tom Musta
---
target-ppc/translate.c | 74
1 files changed, 74 insertions(+), 0 deletions(-)
diff --git a/target
