Am 08.12.2011 06:25, schrieb kha...@kics.edu.pk:
> From: Khansa Butt
>
> This is the team work of Ehsan-ul-Haq, Abdul Qadeer, Abdul Waheed, Khansa Butt
> from HPCN Lab KICS UET Lahore.
> In previous patch set we were including Cavium specific instructions along
> with
> Cavium specifc registers
From: Khansa Butt
This is the team work of Ehsan-ul-Haq, Abdul Qadeer, Abdul Waheed, Khansa Butt
from HPCN Lab KICS UET Lahore.
In previous patch set we were including Cavium specific instructions along with
Cavium specifc registers in UME. Because of these register fields we had to bump
the cpu
> This is the team work of Ehsan-ul-Haq, Abdul Qadeer, Abdul Waheed, Khansa Butt
> from HPCN Lab KICS UET Lahore.
Shouldn't 'Signed-off-by' lines for mentioned persons be present in
the relevant patches if this is a team work?
--
Thanks.
-- Max
On 30 November 2011 11:07, wrote:
> From: Khansa Butt
>
> This is the team work of Ehsan-ul-Haq, Abdul Qadeer, Abdul Waheed, Khansa Butt
> from HPCN Lab KICS UET Lahore.
This cover letter should say:
* which version of this patch set this is (we've had multiple
rounds of it)
* what the cha
From: Khansa Butt
This is the team work of Ehsan-ul-Haq, Abdul Qadeer, Abdul Waheed, Khansa Butt
from HPCN Lab KICS UET Lahore.
configure |1 +
default-configs/mips64-linux-user.mak |1 +
linux-user/main.c | 21 ++-
linux-user/mips64/sys
Hi,
On 07/12/2011 02:09 PM, Khansa Butt wrote:
We have developed Mips64 user mode emulation. In addition we implemented
Cavium specific instruction along with octeon CPU definition. We need your
support to make our contribution public ally available via making it open
source. I tried to resolve
Hi
We have developed Mips64 user mode emulation. In addition we implemented
Cavium specific instruction along with octeon CPU definition. We need your
support to make our contribution public ally available via making it open
source. I tried to resolve the issues pointed out by Aurelien Jarno, Rik
From: Khansa Butt
This is the team work of Ehsan-ul-Haq, Abdul Qadeer, Abdul Waheed, Khansa Butt
from HPCN Lab KICS UET Lahore.
Cavium Networks's Octeon processors are based on MIPS64r2
We have Implemented 27 user mode Cavium specific instructions.
Richard Henderson told me that QEMU does n
