On 10/05/2016 12:21, Peter Xu wrote:
> These two patches are seperated from v6 series of Intel IOMMU IR
> support.
>
> Existing read-only bits of IOAPIC registers are writable. We'd
> better follow the spec to make it read-only. The first patch did
> this.
>
> The 2nd patch emulated real IOAPIC
These two patches are seperated from v6 series of Intel IOMMU IR
support.
Existing read-only bits of IOAPIC registers are writable. We'd
better follow the spec to make it read-only. The first patch did
this.
The 2nd patch emulated real IOAPIC behavior that remote IRR bits are
cleared when configu
