On Tue, 2012-01-10 at 22:45 +0100, Alexander Graf wrote:
> Here's the thing that I don't understand. What exactly is breaking for
> you? I tried -M pseries on a ppc box and on an x86 box and both times
> was able to see /dev/vda.
And mount it and use it ? Here I get the capacity wrong if I don't h
On Tue, 2012-01-10 at 23:41 +0100, Alexander Graf wrote:
>
> No. Libhw shouldn't be able to know anything about target endianness.
> If a device is as brokenly spec'ed as virtio and is coupled to the
> "main CPU endianness", it clearly belongs with the CPU, not into
> libhw.
Ok, can you guys solv
On Tue, 2012-01-10 at 21:46 +0100, Alexander Graf wrote:
> On 10.01.2012, at 21:35, Andreas Färber wrote:
>
> > Am 10.01.2012 21:30, schrieb Alexander Graf:
> >> Maybe the RTAS callbacks really want you to return stuff in little
> endian?
> >
> > IIRC all RTAS callbacks need to be in the same bit
On Wed, 2012-01-11 at 09:04 +1100, Benjamin Herrenschmidt wrote:
> On Tue, 2012-01-10 at 22:45 +0100, Alexander Graf wrote:
> > Here's the thing that I don't understand. What exactly is breaking for
> > you? I tried -M pseries on a ppc box and on an x86 box and both times
> > was able to see /dev/v
On 01/10/2012 05:35 AM, Benjamin Herrenschmidt wrote:
The virtio config area in PIO space is a bit special. The initial
header is little endian but the rest (device specific) is guest
native endian.
The PIO accessors for PCI on machines that don't have native IO ports
assume that all PIO is litt
The virtio config area in PIO space is a bit special. The initial
header is little endian but the rest (device specific) is guest
native endian.
The PIO accessors for PCI on machines that don't have native IO ports
assume that all PIO is little endian, which works fine for everything
except the ab
On 10.01.2012, at 23:52, Alexander Graf wrote:
>
> On 10.01.2012, at 23:49, Benjamin Herrenschmidt wrote:
>
>> On Tue, 2012-01-10 at 23:41 +0100, Alexander Graf wrote:
>>>
>>> No. Libhw shouldn't be able to know anything about target endianness.
>>> If a device is as brokenly spec'ed as virtio
On 10.01.2012, at 23:49, Benjamin Herrenschmidt wrote:
> On Tue, 2012-01-10 at 23:41 +0100, Alexander Graf wrote:
>>
>> No. Libhw shouldn't be able to know anything about target endianness.
>> If a device is as brokenly spec'ed as virtio and is coupled to the
>> "main CPU endianness", it clearly
On 10.01.2012, at 23:02, Anthony Liguori wrote:
> On 01/10/2012 05:35 AM, Benjamin Herrenschmidt wrote:
>> The virtio config area in PIO space is a bit special. The initial
>> header is little endian but the rest (device specific) is guest
>> native endian.
>>
>> The PIO accessors for PCI on mac
On 10.01.2012, at 22:04, Benjamin Herrenschmidt wrote:
> On Tue, 2012-01-10 at 21:46 +0100, Alexander Graf wrote:
>> On 10.01.2012, at 21:35, Andreas Färber wrote:
>>
>>> Am 10.01.2012 21:30, schrieb Alexander Graf:
Maybe the RTAS callbacks really want you to return stuff in little
>> endia
On 10.01.2012, at 21:35, Andreas Färber wrote:
> Am 10.01.2012 21:30, schrieb Alexander Graf:
>> Maybe the RTAS callbacks really want you to return stuff in little endian?
>
> IIRC all RTAS callbacks need to be in the same bitness and endianness
> (MSR LE+SB) as when instantiating RTAS from OF.
Am 10.01.2012 21:30, schrieb Alexander Graf:
> Maybe the RTAS callbacks really want you to return stuff in little endian?
IIRC all RTAS callbacks need to be in the same bitness and endianness
(MSR LE+SB) as when instantiating RTAS from OF.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 904
On 10.01.2012, at 12:35, Benjamin Herrenschmidt wrote:
> The virtio config area in PIO space is a bit special. The initial
> header is little endian but the rest (device specific) is guest
> native endian.
>
> The PIO accessors for PCI on machines that don't have native IO ports
> assume that al
13 matches
Mail list logo
