Pavel Fedin writes:
> Hello!
>
>> > On some architectures TARGET_PAGE_ALIGN() is not enough to get the right
>> > alignment. For example on ARM TARGET_PAGE_BITS is 10 because some old CPUs
>> > support 1K page size, while minimum SMMU page size is 4K.
>> >
>> > This fixes problems like:
>> >
>>
Hello!
> So I think in the end, the one page size we care about is the minimum
> IOMMU granularity. We don't really care about the target page size at
> all and maybe we only care about the host page size for determining what
> might share a page with a sub-page mapping.
Ok, so, in v2 i remove
On Mon, 2015-12-07 at 11:20 +, Peter Maydell wrote:
> On 7 December 2015 at 10:53, Pavel Fedin wrote:
> >> TAGET_PAGE_ALIGN tells us that it *could* be a valid DMA target though.
> >> The VM model is capable of using that as a page size, which means we
> >> assume it is and want to generate a
On 7 December 2015 at 10:53, Pavel Fedin wrote:
>> TAGET_PAGE_ALIGN tells us that it *could* be a valid DMA target though.
>> The VM model is capable of using that as a page size, which means we
>> assume it is and want to generate a fault.
>
> We seem to have looped back. So...
> It is possible
Hello!
> TAGET_PAGE_ALIGN tells us that it *could* be a valid DMA target though.
> The VM model is capable of using that as a page size, which means we
> assume it is and want to generate a fault.
We seem to have looped back. So...
It is possible to fix this according to this assumption. In th
On Thu, 2015-12-03 at 17:36 +, Peter Maydell wrote:
> On 3 December 2015 at 17:19, Alex Williamson
> wrote:
> > On Thu, 2015-12-03 at 16:33 +, Peter Maydell wrote:
> >> On 3 December 2015 at 16:26, Alex Williamson
> >> wrote:
> >> > I feel a lot more comfortable if we limit the scope to
On 3 December 2015 at 17:19, Alex Williamson wrote:
> On Thu, 2015-12-03 at 16:33 +, Peter Maydell wrote:
>> On 3 December 2015 at 16:26, Alex Williamson
>> wrote:
>> > I feel a lot more comfortable if we limit the scope to MMIO regions of
>> > PCI devices. The problems I brought up before
On Thu, 2015-12-03 at 16:33 +, Peter Maydell wrote:
> On 3 December 2015 at 16:26, Alex Williamson
> wrote:
> > I feel a lot more comfortable if we limit the scope to MMIO regions of
> > PCI devices. The problems I brought up before about the device not
> > being able to DMA to a target alig
On 3 December 2015 at 16:26, Alex Williamson wrote:
> I feel a lot more comfortable if we limit the scope to MMIO regions of
> PCI devices. The problems I brought up before about the device not
> being able to DMA to a target aligned RAM address are still a
> possibility that I think we want to c
On Thu, 2015-12-03 at 12:02 +0300, Pavel Fedin wrote:
> Hello!
>
> > > My device defines this BAR to be of 2M size. In this case qemu splits it
> > > up into three
> > > regions:
> > > 1) Region below the MSI-X table (it's called "mmap", for me it's empty
> > > because table offset
> > > is 0
Hello!
> > My device defines this BAR to be of 2M size. In this case qemu splits it
> > up into three
> > regions:
> > 1) Region below the MSI-X table (it's called "mmap", for me it's empty
> > because table offset
> > is 0)
> > 2) MSI-X table itself (20 vectors = 0x0140 bytes for me).
>
On Tue, 2015-11-24 at 18:24 +0300, Pavel Fedin wrote:
> Hello!
>
> > > So, i've got this problem on ARM64. On ARM64 we actually can never have
> > > 1K pages. This page
> > > size was supported only by old 32-bit ARM CPUs, up to ARMv5 IIRC, then it
> > > was dropped. Linux
> > > OS never even
On Wed, 2015-11-25 at 10:00 +0300, Pavel Fedin wrote:
> Hello!
>
> > There are a number of different interesting page sizes here:
> > * the host kernel page size
> > * the target CPU architecture's worst-case smallest page size
> > * the page size the guest kernel is actually using at the mome
Hello!
> There are a number of different interesting page sizes here:
> * the host kernel page size
> * the target CPU architecture's worst-case smallest page size
> * the page size the guest kernel is actually using at the moment
>(consider a 4K-page guest kernel on a 64K-page host kernel
On 18 November 2015 at 22:04, Alex Williamson
wrote:
> On Tue, 2015-11-17 at 10:46 +0300, Pavel Fedin wrote:
>> On some architectures TARGET_PAGE_ALIGN() is not enough to get the right
>> alignment. For example on ARM TARGET_PAGE_BITS is 10 because some old CPUs
>> support 1K page size, while mini
Hello!
> > So, i've got this problem on ARM64. On ARM64 we actually can never have 1K
> > pages. This page
> > size was supported only by old 32-bit ARM CPUs, up to ARMv5 IIRC, then it
> > was dropped. Linux
> > OS never even used it.
> > But, since qemu can emulate those ancient CPUs, TARGET
On Thu, 2015-11-19 at 13:29 +0300, Pavel Fedin wrote:
> Hello!
>
> > > On some architectures TARGET_PAGE_ALIGN() is not enough to get the right
> > > alignment. For example on ARM TARGET_PAGE_BITS is 10 because some old CPUs
> > > support 1K page size, while minimum SMMU page size is 4K.
> > >
>
Hello!
> > On some architectures TARGET_PAGE_ALIGN() is not enough to get the right
> > alignment. For example on ARM TARGET_PAGE_BITS is 10 because some old CPUs
> > support 1K page size, while minimum SMMU page size is 4K.
> >
> > This fixes problems like:
> >
> > 2015-11-17T07:37:42.892265Z qe
On Tue, 2015-11-17 at 10:46 +0300, Pavel Fedin wrote:
> On some architectures TARGET_PAGE_ALIGN() is not enough to get the right
> alignment. For example on ARM TARGET_PAGE_BITS is 10 because some old CPUs
> support 1K page size, while minimum SMMU page size is 4K.
>
> This fixes problems like:
>
On some architectures TARGET_PAGE_ALIGN() is not enough to get the right
alignment. For example on ARM TARGET_PAGE_BITS is 10 because some old CPUs
support 1K page size, while minimum SMMU page size is 4K.
This fixes problems like:
2015-11-17T07:37:42.892265Z qemu-system-aarch64: VFIO_MAP_DMA: -2
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