On Tue, 2 Dec 2014, Leon Alrae wrote:
> > Please note that for this validation I'm using an artificial microMIPS
> > processor that also has an FPU implemented, so that our microMIPS FP
> > support is correctly validated too (I don't really know if there exists
> > any real microMIPS processor
On 18/11/2014 03:59, Maciej W. Rozycki wrote:
> Please note that for this validation I'm using an artificial microMIPS
> processor that also has an FPU implemented, so that our microMIPS FP
> support is correctly validated too (I don't really know if there exists
> any real microMIPS processor
Fix CP0.Config3.ISAOnExc write accesses on microMIPS processors. This
bit is mandatory for any processor that implements the microMIPS
instruction set. This bit is r/w for processors that implement both the
standard MIPS and the microMIPS instruction set. This bit is r/o and
hardwired to 1 if on
