Re: [Qemu-devel] [PATCH] target-arm: Fix incorrect setting of E bit in CPSR

2014-02-28 Thread Peter Maydell
On 28 February 2014 13:40, Peter Maydell wrote: > Commit 4cc35614a moved the exception mask bits out of env->uncached_cpsr > and into env->daif. However the env->daif contents are AArch64 style > mask bits, which include not just the AArch32 AIF bits but also the > new D bit (masks debug exception

[Qemu-devel] [PATCH] target-arm: Fix incorrect setting of E bit in CPSR

2014-02-28 Thread Peter Maydell
Commit 4cc35614a moved the exception mask bits out of env->uncached_cpsr and into env->daif. However the env->daif contents are AArch64 style mask bits, which include not just the AArch32 AIF bits but also the new D bit (masks debug exceptions). This means that when reconstructing the AArch32 CPSR