Re: [Qemu-devel] [PATCH] target/riscv: fix counter-enable checks in ctr()

On Sat, 26 Jan 2019 15:02:56 PST (-0800), xi.w...@gmail.com wrote: Access to a counter in U-mode is permitted only if the corresponding bit is set in both mcounteren and scounteren. The current code ignores mcounteren and checks scounteren only for U-mode access. Signed-off-by: Xi Wang --- ta

[Qemu-devel] [PATCH] target/riscv: fix counter-enable checks in ctr()

Access to a counter in U-mode is permitted only if the corresponding bit is set in both mcounteren and scounteren. The current code ignores mcounteren and checks scounteren only for U-mode access. Signed-off-by: Xi Wang --- target/riscv/csr.c | 12 +--- 1 file changed, 9 insertions(+),