Re: [Qemu-devel] [PATCH] target/openrisc: Fix writes to interrupt mask register

2018-07-01 Thread Richard Henderson
On 07/01/2018 01:12 AM, Stafford Horne wrote: > The interrupt controller mask register (PICMR) allows writing any value > to any of the 32 interrupt mask bits. Writing a 0 masks the interrupt > writing a 1 unmasks (enables) the the interrupt. > > For some reason the old code was or'ing the write

[Qemu-devel] [PATCH] target/openrisc: Fix writes to interrupt mask register

2018-07-01 Thread Stafford Horne
The interrupt controller mask register (PICMR) allows writing any value to any of the 32 interrupt mask bits. Writing a 0 masks the interrupt writing a 1 unmasks (enables) the the interrupt. For some reason the old code was or'ing the write values to the PICMR meaning it was not possible to ever