On 9/17/19 12:56 PM, Peter Maydell wrote:
> On Tue, 17 Sep 2019 at 09:43, Luc Michel wrote:
>>
>> On 9/13/19 9:26 AM, Luc Michel wrote:
>>> Hi Peter,
>>>
>>> On 9/12/19 6:03 PM, Peter Maydell wrote:
I think we need to check through the TRMs to confirm which CPUs use
which format for t
On Tue, 17 Sep 2019 at 09:43, Luc Michel wrote:
>
> On 9/13/19 9:26 AM, Luc Michel wrote:
> > Hi Peter,
> >
> > On 9/12/19 6:03 PM, Peter Maydell wrote:
> >> I think we need to check through the TRMs to confirm which CPUs use
> >> which format for the CBAR, and have a different feature bit for the
On 9/13/19 9:26 AM, Luc Michel wrote:
> Hi Peter,
>
> On 9/12/19 6:03 PM, Peter Maydell wrote:
>> On Thu, 12 Sep 2019 at 12:01, Luc Michel wrote:
>>>
>>> For AArch64 CPUs with a CBAR register, we have two views for it:
>>> - in AArch64 state, the CBAR_EL1 register (S3_1_C15_C3_0), returns the
>
Hi Peter,
On 9/12/19 6:03 PM, Peter Maydell wrote:
> On Thu, 12 Sep 2019 at 12:01, Luc Michel wrote:
>>
>> For AArch64 CPUs with a CBAR register, we have two views for it:
>> - in AArch64 state, the CBAR_EL1 register (S3_1_C15_C3_0), returns the
>> full 64 bits CBAR value
>> - in AArch32
On Thu, 12 Sep 2019 at 12:01, Luc Michel wrote:
>
> For AArch64 CPUs with a CBAR register, we have two views for it:
> - in AArch64 state, the CBAR_EL1 register (S3_1_C15_C3_0), returns the
> full 64 bits CBAR value
> - in AArch32 state, the CBAR register (cp15, opc1=1, CRn=15, CRm=3, opc2
For AArch64 CPUs with a CBAR register, we have two views for it:
- in AArch64 state, the CBAR_EL1 register (S3_1_C15_C3_0), returns the
full 64 bits CBAR value
- in AArch32 state, the CBAR register (cp15, opc1=1, CRn=15, CRm=3, opc2=0)
returns a 32 bits view such that:
CBAR = CBAR
