Richard Henderson writes:
> On 03/07/2017 08:00 AM, Paolo Bonzini wrote:
>>> Signed-off-by: Richard Henderson
>>> ---
>>> This is similar to the patch that I saw go by for MIPS.
>>>
>>> I hadn't noticed any problems caused by this lack of locking. This may
>>> be because interrupts cannot be d
On 03/07/2017 08:00 AM, Paolo Bonzini wrote:
Signed-off-by: Richard Henderson
---
This is similar to the patch that I saw go by for MIPS.
I hadn't noticed any problems caused by this lack of locking. This may
be because interrupts cannot be delivered while in PALmode while these
registers are
> Signed-off-by: Richard Henderson
> ---
> This is similar to the patch that I saw go by for MIPS.
>
> I hadn't noticed any problems caused by this lack of locking. This may
> be because interrupts cannot be delivered while in PALmode while these
> registers are being manipulated. However, it's
Signed-off-by: Richard Henderson
---
This is similar to the patch that I saw go by for MIPS.
I hadn't noticed any problems caused by this lack of locking. This may
be because interrupts cannot be delivered while in PALmode while these
registers are being manipulated. However, it's always better