Re: [Qemu-devel] [PATCH] pci: honor PCI_COMMAND_MEMORY

2017-07-18 Thread Michael S. Tsirkin
On Tue, Jul 18, 2017 at 10:23:06AM +0300, Dmitry Fleytman wrote: > On 17 Jul 2017, at 19:59 PM, Michael S. Tsirkin wrote: > > > On Mon, Jul 17, 2017 at 03:48:03PM +0300, Dmitry Fleytman wrote: > > Am I understand correctly that there are no special cases for > IDE controller

Re: [Qemu-devel] [PATCH] pci: honor PCI_COMMAND_MEMORY

2017-07-18 Thread Dmitry Fleytman
On 17 Jul 2017, at 19:59 PM, Michael S. Tsirkin wrote: > > On Mon, Jul 17, 2017 at 03:48:03PM +0300, Dmitry Fleytman wrote: >> Am I understand correctly that there are no special cases for >> IDE controllers, i.e. bus master bit must be set by SW same >> way as for other PCI devices? > > Bus mas

Re: [Qemu-devel] [PATCH] pci: honor PCI_COMMAND_MEMORY

2017-07-17 Thread Michael S. Tsirkin
On Mon, Jul 17, 2017 at 03:48:03PM +0300, Dmitry Fleytman wrote: > Am I understand correctly that there are no special cases for > IDE controllers, i.e. bus master bit must be set by SW same > way as for other PCI devices? Bus mastering is typically enabled by the driver. E.g. under linux: static

Re: [Qemu-devel] [PATCH] pci: honor PCI_COMMAND_MEMORY

2017-07-17 Thread Marcel Apfelbaum
On 17/07/2017 15:48, Dmitry Fleytman wrote: On 16 Jul 2017, at 19:56 PM, Marcel Apfelbaum > wrote: On 16/07/2017 11:29, Dmitry Fleytman wrote: According to PCI spec. bit 1 of command register (PCI_COMMAND_MEMORY) controls a device's response to memory space accesses. A

Re: [Qemu-devel] [PATCH] pci: honor PCI_COMMAND_MEMORY

2017-07-17 Thread Dmitry Fleytman
On 16 Jul 2017, at 19:56 PM, Marcel Apfelbaum wrote: > > On 16/07/2017 11:29, Dmitry Fleytman wrote: >> According to PCI spec. bit 1 of command >> register (PCI_COMMAND_MEMORY) controls >> a device's response to memory space accesses. >> A value of 0 disables the device response. >> A value of 1

Re: [Qemu-devel] [PATCH] pci: honor PCI_COMMAND_MEMORY

2017-07-16 Thread Marcel Apfelbaum
On 16/07/2017 11:29, Dmitry Fleytman wrote: According to PCI spec. bit 1 of command register (PCI_COMMAND_MEMORY) controls a device's response to memory space accesses. A value of 0 disables the device response. A value of 1 allows the device to respond to memory space accesses. Hi Dmitry,

[Qemu-devel] [PATCH] pci: honor PCI_COMMAND_MEMORY

2017-07-16 Thread Dmitry Fleytman
According to PCI spec. bit 1 of command register (PCI_COMMAND_MEMORY) controls a device's response to memory space accesses. A value of 0 disables the device response. A value of 1 allows the device to respond to memory space accesses. Current behavior introduced by commit commit 1c380f9460522f