On 05/11/2014 20:16, Maciej W. Rozycki wrote:
> Now as to CP0.Status.CU1, while fixing the 5Kc and 5KEc processors is an
> obvious change, I think the removal of the extra check may not be such.
> The thing is in the original architecture -- and it still stands for CP2
> -- these bits used to
On Wed, 5 Nov 2014, Leon Alrae wrote:
> > qemu-umips-cu1-ex.diff
> > Index: qemu-git-trunk/target-mips/translate.c
> > ===
> > --- qemu-git-trunk.orig/target-mips/translate.c 2014-10-27
> > 04:26:57.0 +
> > +++ qemu-g
On 03/11/2014 19:08, Maciej W. Rozycki wrote:
> Make microMIPS FP branches respect CP0.Status.CU1 and trap with a
> Coprocessor Unusable exception if COP1 has been disabled; also trap if
> no FPU is present at all.
>
> Standard MIPS FP instruction encodings have a more regular structure and
> b
Make microMIPS FP branches respect CP0.Status.CU1 and trap with a
Coprocessor Unusable exception if COP1 has been disabled; also trap if
no FPU is present at all.
Standard MIPS FP instruction encodings have a more regular structure and
branches are covered with a single umbrella along other ins
