On 08/02/2016 06:05 PM, John Snow wrote:
ATA8-APT defines the state transitions for both a host controller and
for the hardware device during the lifecycle of a DMA transfer, in
section 9.7 "DMA command protocol."
One of the interesting tidbits here is that when a device transitions
from DDMA0
Am 03.08.2016 um 15:19 schrieb John Snow:
> I also have to admit that I misread the report; I was under the
> impression that this was affecting Linux/Windows guests in some
> capacity, but re-reading the report I realize that you meant that you
> have observed behavior with a test case on Windows
On 08/03/2016 05:24 AM, Kevin Wolf wrote:
Am 03.08.2016 um 07:06 hat Stefan Weil geschrieben:
Am 03.08.2016 um 00:05 schrieb John Snow:
ATA8-APT defines the state transitions for both a host controller and
for the hardware device during the lifecycle of a DMA transfer, in
section 9.7 "DMA com
Am 03.08.2016 um 07:06 hat Stefan Weil geschrieben:
> Am 03.08.2016 um 00:05 schrieb John Snow:
> > ATA8-APT defines the state transitions for both a host controller and
> > for the hardware device during the lifecycle of a DMA transfer, in
> > section 9.7 "DMA command protocol."
> >
> > One of th
Am 03.08.2016 um 00:05 schrieb John Snow:
> ATA8-APT defines the state transitions for both a host controller and
> for the hardware device during the lifecycle of a DMA transfer, in
> section 9.7 "DMA command protocol."
>
> One of the interesting tidbits here is that when a device transitions
> f
ATA8-APT defines the state transitions for both a host controller and
for the hardware device during the lifecycle of a DMA transfer, in
section 9.7 "DMA command protocol."
One of the interesting tidbits here is that when a device transitions
from DDMA0 ("Prepare state") to DDMA1 ("Data_Transfer S
