From: Rabin Vincent
The first enable set/clear register (which controls the PPIs and SGIs)
is supposed to be banked for each processor. Currently it is just
handled globally and this prevents recent SMP Linux kernels from
booting, because CPU0 stops receiving localtimer interrupts when CPU1
disa
On 1 November 2011 22:31, Peter Maydell wrote:
> On 28 October 2011 18:40, Rabin Vincent wrote:
>> The first enable set/clear register (which controls the PPIs and SGIs)
>> is supposed to be banked for each processor. Currently it is just
>> handled globally and this prevents recent SMP Linux ke
On 28 October 2011 18:40, Rabin Vincent wrote:
> The first enable set/clear register (which controls the PPIs and SGIs)
> is supposed to be banked for each processor. Currently it is just
> handled globally and this prevents recent SMP Linux kernels from
> booting, because CPU0 stops receiving lo
The first enable set/clear register (which controls the PPIs and SGIs)
is supposed to be banked for each processor. Currently it is just
handled globally and this prevents recent SMP Linux kernels from
booting, because CPU0 stops receiving localtimer interrupts when CPU1
disables them locally.
To
