On 12/30/19 6:11 PM, LIU Zhiwei wrote:
>
> However It's not clear when use tcg_gen_gvec_*_ptr or tcg_gen_gvec_ool. I
> think
> the meaning of oprsz is the
> the bits of active elements. Therefore , oprsz is 8 * env->vext.vl in RISC-V
> and it can't be fetched from
> TB_FLAGS like SVE.
>
> Pro
On 2019/12/28 9:14, Richard Henderson wrote:
On 12/25/19 8:36 PM, LIU Zhiwei wrote:
struct {
uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16);
target_ulong vxrm;
target_ulong vxsat;
target_ulong vl;
target_ulong vstart;
target_ulong
On 12/25/19 8:36 PM, LIU Zhiwei wrote:
> struct {
>
> uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16);
> target_ulong vxrm;
> target_ulong vxsat;
> target_ulong vl;
> target_ulong vstart;
> target_ulong vtype;
> } vext;
>
> Is it OK?
I don
On 2019/12/20 4:38, Richard Henderson wrote:
On 12/18/19 11:11 PM, LIU Zhiwei wrote:
I'm sorry that it's really hard to absorb your opinion. I don't know why clang
will fail
when index beyond the end of vreg[n] into vreg[n+1].
I thought sure one of the address sanitizer checks would detect ar
On 12/18/19 11:11 PM, LIU Zhiwei wrote:
> I'm sorry that it's really hard to absorb your opinion. I don't know why clang
> will fail
>
> when index beyond the end of vreg[n] into vreg[n+1].
I thought sure one of the address sanitizer checks would detect array bounds
overrun. But it becomes irrel
Hi Richard，
Sorry to reply so late.
Upstream is really difficult . I was really frustrated to recieve so
many difficult comments.
It is hard for me to absorb them and will take a lot of time to fixup.
Now I will move on.
On 2019/8/29 2:54, Richard Henderson wrote:
On 8/27/19 7:36 PM, liuz
On 9/2/19 2:43 AM, liuzhiwei wrote:
>> This is most definitely not the correct way to implement first-fault.
>>
>> You need to have a look at target/arm/sve_helper.c, e.g. sve_ldff1_r,
>> where we test pages for validity with tlb_vaddr_to_host.
> Why should test pages for validity? If there is a p
On 9/2/19 12:45 AM, liuzhiwei wrote:
>
> On 2019/8/29 下午11:09, Richard Henderson wrote:
>> On 8/29/19 5:45 AM, liuzhiwei wrote:
>>> Even in qemu, it may be some situations that VSTART != 0. For example, a
>>> load
>>> instruction leads to a page fault exception in a middle position. If VSTART
>
On 2019/8/29 上午2:54, Richard Henderson wrote:
On 8/27/19 7:36 PM, liuzhiwei wrote:
Change-Id: I3cf891bc400713b95f47ecca82b1bf773f3dcb25
Signed-off-by: liuzhiwei
---
fpu/softfloat.c | 119 +
include/fpu/softfloat.h | 4 +
linux-user/riscv/cpu_l
On 2019/8/29 下午11:09, Richard Henderson wrote:
On 8/29/19 5:45 AM, liuzhiwei wrote:
Even in qemu, it may be some situations that VSTART != 0. For example, a load
instruction leads to a page fault exception in a middle position. If VSTART ==
0, some elements that had been loaded before the ex
On 2019/8/29 下午11:14, Richard Henderson wrote:
On 8/29/19 5:00 AM, liuzhiwei wrote:
Maybe there is some better test method or some forced test cases in QEMU. Could
you give me some advice for testing?
If you have hardware, or another simulator, RISU is very good
for testing these sorts of thi
On 2019/8/30 上午5:50, Alistair Francis wrote:
On Thu, Aug 29, 2019 at 5:05 AM liuzhiwei wrote:
On 2019/8/29 上午5:34, Alistair Francis wrote:
On Wed, Aug 28, 2019 at 12:04 AM liuzhiwei wrote:
Change-Id: I3cf891bc400713b95f47ecca82b1bf773f3dcb25
Signed-off-by: liuzhiwei
---
fpu/softfloat.c
On Fri, Aug 30, 2019 at 2:06 AM Alex Bennée wrote:
>
>
> Alistair Francis writes:
>
> > On Thu, Aug 29, 2019 at 5:05 AM liuzhiwei wrote:
> >>
> >> On 2019/8/29 上午5:34, Alistair Francis wrote:
> >> > On Wed, Aug 28, 2019 at 12:04 AM liuzhiwei wrote:
> >> >> Change-Id: I3cf891bc400713b95f47ecca82
Alistair Francis writes:
> On Thu, Aug 29, 2019 at 5:05 AM liuzhiwei wrote:
>>
>> On 2019/8/29 上午5:34, Alistair Francis wrote:
>> > On Wed, Aug 28, 2019 at 12:04 AM liuzhiwei wrote:
>> >> Change-Id: I3cf891bc400713b95f47ecca82b1bf773f3dcb25
>> >> Signed-off-by: liuzhiwei
>> >> ---
>> >> fp
On Thu, Aug 29, 2019 at 5:05 AM liuzhiwei wrote:
>
> On 2019/8/29 上午5:34, Alistair Francis wrote:
> > On Wed, Aug 28, 2019 at 12:04 AM liuzhiwei wrote:
> >> Change-Id: I3cf891bc400713b95f47ecca82b1bf773f3dcb25
> >> Signed-off-by: liuzhiwei
> >> ---
> >> fpu/softfloat.c
29.08.2019. 15.02, "liuzhiwei" је написао/ла:
>
>
> On 2019/8/29 上午3:20, Aleksandar Markovic wrote:
>>
>>
>>
>> > On Wed, Aug 28, 2019 at 9:04 AM liuzhiwei wrote:
>>>
>>> Change-Id: I3cf891bc400713b95f47ecca82b1bf773f3dcb25
>>> Signed-off-by: liuzhiwei
>>> ---
>>
>>
>> Such large patch and "Chan
On 8/29/19 5:45 AM, liuzhiwei wrote:
> Even in qemu, it may be some situations that VSTART != 0. For example, a load
> instruction leads to a page fault exception in a middle position. If VSTART ==
> 0, some elements that had been loaded before the exception will be loaded
> once
> again.
Alter
On 8/29/19 5:00 AM, liuzhiwei wrote:
> Maybe there is some better test method or some forced test cases in QEMU.
> Could
> you give me some advice for testing?
If you have hardware, or another simulator, RISU is very good
for testing these sorts of things.
See https://git.linaro.org/people/pmayd
Hi, Alex
On 2019/8/28 下午5:08, Alex Bennée wrote:
liuzhiwei writes:
Change-Id: I3cf891bc400713b95f47ecca82b1bf773f3dcb25
Signed-off-by: liuzhiwei
---
fpu/softfloat.c | 119 +
include/fpu/softfloat.h | 4 +
Changes to softfloat should be in a s
On 2019/8/29 上午4:43, Richard Henderson wrote:
On 8/28/19 11:54 AM, Richard Henderson wrote:
But it might be reasonable to include (VSTART == 0 && VL == VLMAX) as a
single bit.
BTW, it is reasonable to check VSTART == 0 always. Quoting the spec:
# Implementations are permitted to raise illeg
On 2019/8/29 上午5:34, Alistair Francis wrote:
On Wed, Aug 28, 2019 at 12:04 AM liuzhiwei wrote:
Change-Id: I3cf891bc400713b95f47ecca82b1bf773f3dcb25
Signed-off-by: liuzhiwei
---
fpu/softfloat.c | 119 +
include/fpu/softfloat.h | 4 +
linux-user/
On Wed, Aug 28, 2019 at 12:04 AM liuzhiwei wrote:
>
> Change-Id: I3cf891bc400713b95f47ecca82b1bf773f3dcb25
> Signed-off-by: liuzhiwei
> ---
> fpu/softfloat.c | 119 +
> include/fpu/softfloat.h | 4 +
> linux-user/riscv/cpu_loop.c | 8
On 8/28/19 11:54 AM, Richard Henderson wrote:
> But it might be reasonable to include (VSTART == 0 && VL == VLMAX) as a
> single bit.
BTW, it is reasonable to check VSTART == 0 always. Quoting the spec:
# Implementations are permitted to raise illegal instruction exceptions
# when attempting to
On 8/27/19 7:36 PM, liuzhiwei wrote:
> Change-Id: I3cf891bc400713b95f47ecca82b1bf773f3dcb25
> Signed-off-by: liuzhiwei
> ---
> fpu/softfloat.c | 119 +
> include/fpu/softfloat.h | 4 +
> linux-user/riscv/cpu_loop.c | 8 +-
> target/ris
On 8/28/19 2:08 AM, Alex Bennée wrote:
> If you want to do vectors I suggest you look at the TCGvec types for
> passing pointers to vector registers to helpers. In this case you will
> want to ensure your vector registers are properly aligned.
The risc-v vector extension is very different from any
liuzhiwei writes:
> Change-Id: I3cf891bc400713b95f47ecca82b1bf773f3dcb25
> Signed-off-by: liuzhiwei
> ---
> fpu/softfloat.c | 119 +
> include/fpu/softfloat.h | 4 +
Changes to softfloat should be in a separate patch, but see bellow.
> linux-use
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