On 08/04/2011 12:34 PM, Elie Richa wrote:
bump.
Anybody have opinions on this?
I can provide a more thorough explanation of the problem if needed. I
wrote the test case in Ada for an MPC8641D processor (2 e600 cores) on
a board that is not yet submitted to the list, therefore I cannot
provide
bump.
Anybody have opinions on this?
I can provide a more thorough explanation of the problem if needed. I
wrote the test case in Ada for an MPC8641D processor (2 e600 cores) on a
board that is not yet submitted to the list, therefore I cannot provide
a ready to run binary. I can submit my boa
In the current emulation of the load-and-reserve (lwarx) and
store-conditional (stwcx.) instructions, the internal reservation
mechanism is taken into account, however each CPU has its own
reservation information and this information is not synchronized between
CPUs to perform proper synchronizatio
