With more information at hand with the reference manual from Freescale
http://cache.nxp.com/files/32bit/doc/ref_manual/SPEPEM.pdf , I was able to
revisit my patch and figure out what is actually going on.
Before applying any patch, efscmp* instructions in QEMU set crD values as
(0b0100 << 2) = 0b1
Adding some more basis to the patch:
I received some documentation from Freescale support relating to this:
Signal Processing Engine (SPE) Programming Environments Manual:
http://cache.nxp.com/files/32bit/doc/ref_manual/SPEPEM.pdf.
Relevant info is on page #113.
According to the documentation, t
Hi Everyone,
Please find attached a patch which fixes handling in QEMU PPC e500v1 for efscmp*
instructions. This was the cause of over 400 FAILs for this CPU while running
GCC testsuite, which have been fixed.
Value for Condition Registers (CR) being set in QEMU was different from
the value obser
