In the end it was just incorrect alignment for my vector table
On Thu, Aug 23, 2018 at 4:01 PM Christopher Friedt
wrote:
> On Thu., Aug. 23, 2018, 3:50 p.m. Christopher Friedt,
> wrote:
>> On Thu., Aug. 23, 2018, 2:20 p.m. Peter Maydell,
>> wrote:
>>> On 23 August 2018 at 17:36, Christopher Friedt
>>> wrote:
>>>
>>> happen to have a copy on your lake, b
On Thu., Aug. 23, 2018, 3:50 p.m. Christopher Friedt,
wrote:
>
>
> On Thu., Aug. 23, 2018, 2:20 p.m. Peter Maydell,
> wrote:
>
>> On 23 August 2018 at 17:36, Christopher Friedt
>> wrote:
>>
>> happen to have a copy on your lake, but the short answer
>> is that bit 1 must be set, exactly because
On Thu., Aug. 23, 2018, 2:20 p.m. Peter Maydell,
wrote:
> On 23 August 2018 at 17:36, Christopher Friedt
> wrote:
>
> Hi; thanks for your patch, but I don't think it is correct.
> What it does is to make QEMU ignore the T bit in the xPSR.
> The architecture says that what should happen is that a
On 23 August 2018 at 17:36, Christopher Friedt wrote:
> I hope this message finds you well, as I'm currently on a lake in the
> middle of nowhere relying on my flaky cellular connection. Roaming
> sucks. In any case, I found a bug while trying to execute the "svc 0"
> instruction for cortex-m3.
>
Hi list,
I hope this message finds you well, as I'm currently on a lake in the
middle of nowhere relying on my flaky cellular connection. Roaming
sucks. In any case, I found a bug while trying to execute the "svc 0"
instruction for cortex-m3.
A UsageFault (EXCP_INVSTATE) is injected at
target/arm
