Hi
The patch below adds support for 5Kc, 5Kf and 20Kc CPU, ie all the CPU
that can be found on a CoreLV card. Note that MIPS performance counters
are not yet available in QEMU, so the corresponding configuration bit of
the 20Kc CPU is not set.
This patch also fixes the Status_rw_bitmask value of the R4000 CPU, as
the PX bit should be writeable on this CPU.
Finally it changes the default 64-bit CPU of the Malta board to a 5Kf
one from a R4000 one. The R4000 is not really a good default choice, as
it does not have the wait instruction, so QEMU uses all the host CPU
with this target CPU.
Bye,
Aurelien
Index: hw/mips_malta.c
===================================================================
RCS file: /sources/qemu/qemu/hw/mips_malta.c,v
retrieving revision 1.27
diff -u -d -p -r1.27 mips_malta.c
--- hw/mips_malta.c 4 May 2007 14:34:34 -0000 1.27
+++ hw/mips_malta.c 21 May 2007 04:22:37 -0000
@@ -779,7 +779,7 @@ void mips_malta_init (int ram_size, int
/* init CPUs */
if (cpu_model == NULL) {
#ifdef TARGET_MIPS64
- cpu_model = "R4000";
+ cpu_model = "5Kf";
#else
cpu_model = "24Kf";
#endif
Index: target-mips/translate_init.c
===================================================================
RCS file: /sources/qemu/qemu/target-mips/translate_init.c,v
retrieving revision 1.9
diff -u -d -p -r1.9 translate_init.c
--- target-mips/translate_init.c 13 May 2007 13:49:44 -0000 1.9
+++ target-mips/translate_init.c 21 May 2007 04:22:38 -0000
@@ -145,7 +145,46 @@ static mips_def_t mips_defs[] =
.CP0_Config3 = MIPS_CONFIG3,
.SYNCI_Step = 16,
.CCRes = 2,
- .Status_rw_bitmask = 0x3678FFFF,
+ .Status_rw_bitmask = 0x36F8FFFF,
+ .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
+ (1 << FCR0_D) | (1 << FCR0_S) |
+ (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
+ },
+ {
+ .name = "5Kc",
+ .CP0_PRid = 0x00018100,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
+ .CP0_Config1 = MIPS_CONFIG1 | (47 << CP0C1_MMU),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .SYNCI_Step = 16,
+ .CCRes = 2,
+ .Status_rw_bitmask = 0x32F8FFFF,
+ },
+ {
+ .name = "5Kf",
+ .CP0_PRid = 0x00018100,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .SYNCI_Step = 16,
+ .CCRes = 2,
+ .Status_rw_bitmask = 0x36F8FFFF,
+ .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
+ (1 << FCR0_D) | (1 << FCR0_S) |
+ (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
+ },
+ {
+ .name = "20Kc",
+ .CP0_PRid = 0x00018200,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | (0x2 << CP0C0_VI),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .SYNCI_Step = 16,
+ .CCRes = 2,
+ .Status_rw_bitmask = 0x36FBFFFF,
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
(1 << FCR0_D) | (1 << FCR0_S) |
(0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' [EMAIL PROTECTED] | [EMAIL PROTECTED]
`- people.debian.org/~aurel32 | www.aurel32.net
