On 30/04/2025 02.00, Nicholas Piggin wrote:
On Thu Apr 24, 2025 at 6:25 PM AEST, Thomas Huth wrote:
On 08/04/2025 14.45, Nicholas Piggin wrote:
The per-core SCRATCH0-7 registers are shared between big cores, which
was missed in the big-core implementation. It is difficult to model
well with the
On Thu Apr 24, 2025 at 6:25 PM AEST, Thomas Huth wrote:
> On 08/04/2025 14.45, Nicholas Piggin wrote:
>> The per-core SCRATCH0-7 registers are shared between big cores, which
>> was missed in the big-core implementation. It is difficult to model
>> well with the big-core == 2xPnvCore scheme we move
On 08/04/2025 14.45, Nicholas Piggin wrote:
The per-core SCRATCH0-7 registers are shared between big cores, which
was missed in the big-core implementation. It is difficult to model
well with the big-core == 2xPnvCore scheme we moved to, this fix
uses the even PnvCore to store the scrach data.
A
The per-core SCRATCH0-7 registers are shared between big cores, which
was missed in the big-core implementation. It is difficult to model
well with the big-core == 2xPnvCore scheme we moved to, this fix
uses the even PnvCore to store the scrach data.
Also remove a stray log message that came in wi
