On Thu, 7 Apr 2022 21:07:06 +
Tong Zhang wrote:
> On 4/4/22 08:14, Jonathan Cameron wrote:
> > From: Jonathan Cameron
> >
> >
> > +static MemTxResult cxl_read_cfmws(void *opaque, hwaddr addr, uint64_t
> > *data,
> > + unsigned size, MemTxAttrs attrs)
> > +{
On 4/4/22 08:14, Jonathan Cameron wrote:
> From: Jonathan Cameron
>
>
> +static MemTxResult cxl_read_cfmws(void *opaque, hwaddr addr, uint64_t *data,
> + unsigned size, MemTxAttrs attrs)
> +{
> +CXLFixedWindow *fw = opaque;
> +PCIDevice *d;
> +
> +d =
From: Jonathan Cameron
These memops perform interleave decoding, walking down the
CXL topology from CFMWS described host interleave
decoder via CXL host bridge HDM decoders, through the CXL
root ports and finally call CXL type 3 specific read and write
functions.
Note that, whilst functional the
