Re: [PATCH v8 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

On 6/28/22 18:17, Anup Patel wrote: > We should write transformed instruction encoding of the trapped > instruction in [m|h]tinst CSR at time of taking trap as defined > by the RISC-V privileged specification v1.12. > > Reviewed-by: Alistair Francis > Signed-off-by: Anup Patel > --- > target/r

[PATCH v8 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

We should write transformed instruction encoding of the trapped instruction in [m|h]tinst CSR at time of taking trap as defined by the RISC-V privileged specification v1.12. Reviewed-by: Alistair Francis Signed-off-by: Anup Patel --- target/riscv/cpu.h| 5 + target/riscv/cpu_helper.c