Re: [PATCH v7 03/10] target/riscv: allow MISA writes as experimental

2023-03-09 Thread Daniel Henrique Barboza
On 3/9/23 03:11, LIU Zhiwei wrote: On 2023/2/23 2:51, Daniel Henrique Barboza wrote: At this moment, and apparently since ever, we have no way of enabling RISCV_FEATURE_MISA. This means that all the code from write_misa(), all the nuts and bolts that handles how to properly write this CSR, h

Re: [PATCH v7 03/10] target/riscv: allow MISA writes as experimental

2023-03-08 Thread LIU Zhiwei
On 2023/2/23 2:51, Daniel Henrique Barboza wrote: At this moment, and apparently since ever, we have no way of enabling RISCV_FEATURE_MISA. This means that all the code from write_misa(), all the nuts and bolts that handles how to properly write this CSR, has always been a no-op as well because

Re: [PATCH v7 03/10] target/riscv: allow MISA writes as experimental

2023-02-28 Thread LIU Zhiwei
On 2023/2/23 2:51, Daniel Henrique Barboza wrote: At this moment, and apparently since ever, we have no way of enabling RISCV_FEATURE_MISA. This means that all the code from write_misa(), all the nuts and bolts that handles how to properly write this CSR, has always been a no-op as well because

Re: [PATCH v7 03/10] target/riscv: allow MISA writes as experimental

2023-02-28 Thread liweiwei
On 2023/2/23 02:51, Daniel Henrique Barboza wrote: At this moment, and apparently since ever, we have no way of enabling RISCV_FEATURE_MISA. This means that all the code from write_misa(), all the nuts and bolts that handles how to properly write this CSR, has always been a no-op as well becaus

Re: [PATCH v7 03/10] target/riscv: allow MISA writes as experimental

2023-02-28 Thread Bin Meng
On Thu, Feb 23, 2023 at 2:53 AM Daniel Henrique Barboza wrote: > > At this moment, and apparently since ever, we have no way of enabling > RISCV_FEATURE_MISA. This means that all the code from write_misa(), all > the nuts and bolts that handles how to properly write this CSR, has > always been a n

Re: [PATCH v7 03/10] target/riscv: allow MISA writes as experimental

2023-02-22 Thread Andrew Jones
On Wed, Feb 22, 2023 at 03:51:58PM -0300, Daniel Henrique Barboza wrote: > At this moment, and apparently since ever, we have no way of enabling > RISCV_FEATURE_MISA. This means that all the code from write_misa(), all > the nuts and bolts that handles how to properly write this CSR, has > always b

Re: [PATCH v7 03/10] target/riscv: allow MISA writes as experimental

2023-02-22 Thread liweiwei
On 2023/2/23 02:51, Daniel Henrique Barboza wrote: At this moment, and apparently since ever, we have no way of enabling RISCV_FEATURE_MISA. This means that all the code from write_misa(), all the nuts and bolts that handles how to properly write this CSR, has always been a no-op as well becaus

[PATCH v7 03/10] target/riscv: allow MISA writes as experimental

2023-02-22 Thread Daniel Henrique Barboza
At this moment, and apparently since ever, we have no way of enabling RISCV_FEATURE_MISA. This means that all the code from write_misa(), all the nuts and bolts that handles how to properly write this CSR, has always been a no-op as well because write_misa() will always exit earlier. This seems to