Re: [PATCH v6 20/22] target/riscv: Adjust scalar reg in vector with XLEN

2022-01-18 Thread Alistair Francis
On Thu, Jan 13, 2022 at 10:20 PM LIU Zhiwei wrote: > > When sew <= 32bits, not need to extend scalar reg. > When sew > 32bits, if xlen is less that sew, we should sign extend > the scalar register, except explicitly specified by the spec. > > Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Franc

[PATCH v6 20/22] target/riscv: Adjust scalar reg in vector with XLEN

2022-01-13 Thread LIU Zhiwei
When sew <= 32bits, not need to extend scalar reg. When sew > 32bits, if xlen is less that sew, we should sign extend the scalar register, except explicitly specified by the spec. Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvv.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 dele