Hi Zhao,
On 2/20/2025 6:11 AM, Zhao Liu wrote:
+static const CPUCaches epyc_turin_cache_info = {
+.l1d_cache = &(CPUCacheInfo) {
+.type = DATA_CACHE,
+.level = 1,
+.size = 48 * KiB,
+.line_size = 64,
+.associativity = 12,
+.partitions = 1,
+
> +static const CPUCaches epyc_turin_cache_info = {
> +.l1d_cache = &(CPUCacheInfo) {
> +.type = DATA_CACHE,
> +.level = 1,
> +.size = 48 * KiB,
> +.line_size = 64,
> +.associativity = 12,
> +.partitions = 1,
> +.sets = 64,
> +.lin
Add the support for AMD EPYC zen 5 processors (EPYC-Turin).
Add the following new feature bits on top of the feature bits from
the previous generation EPYC models.
movdiri : Move Doubleword as Direct Store Instruction
movdir64b : Move 64 Bytes as Direct Store Instruction
avx
