Re: [PATCH v5 3/5] target/riscv: add support for svnapot extension

在 2022/1/18 上午11:32, Anup Patel 写道: On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li wrote: - add PTE_N bit - add PTE_N bit check for inner PTE - update address translation to support 64KiB continuous region (napot_bits = 4) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Cc: Anup Patel I

Re: [PATCH v5 3/5] target/riscv: add support for svnapot extension

On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li wrote: > > - add PTE_N bit > - add PTE_N bit check for inner PTE > - update address translation to support 64KiB continuous region (napot_bits = > 4) > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > Cc: Anup Patel I did review this patch

[PATCH v5 3/5] target/riscv: add support for svnapot extension

- add PTE_N bit - add PTE_N bit check for inner PTE - update address translation to support 64KiB continuous region (napot_bits = 4) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Cc: Anup Patel --- target/riscv/cpu.c| 2 ++ target/riscv/cpu.h| 1 + target/riscv/cpu_bi