Re: [PATCH v5 17/60] target/riscv: vector single-width integer multiply instructions

On 2020/3/14 14:52, Richard Henderson wrote: On 3/12/20 7:58 AM, LIU Zhiwei wrote: +static int64_t do_mulhsu_d(int64_t s2, uint64_t s1) +{ +uint64_t hi_64, lo_64, abs_s2 = s2; + +if (s2 < 0) { +abs_s2 = -s2; +} +mulu64(&lo_64, &hi_64, abs_s2, s1); +if ((int64_t)(s2

Re: [PATCH v5 17/60] target/riscv: vector single-width integer multiply instructions

On 3/12/20 7:58 AM, LIU Zhiwei wrote: > +static int64_t do_mulhsu_d(int64_t s2, uint64_t s1) > +{ > +uint64_t hi_64, lo_64, abs_s2 = s2; > + > +if (s2 < 0) { > +abs_s2 = -s2; > +} > +mulu64(&lo_64, &hi_64, abs_s2, s1); > +if ((int64_t)(s2 ^ s1) < 0) { Why would the sign

[PATCH v5 17/60] target/riscv: vector single-width integer multiply instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 8 ++ target/riscv/insn_trans/trans_rvv.inc.c | 10 ++ target/riscv/vector_helper.c| 147 4 files changed, 198 insertions(+) diff