Re: [PATCH v5 16/20] intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2

2024-12-03 Thread Jason Wang
On Mon, Nov 11, 2024 at 4:39 PM Zhenzhong Duan wrote: > > According to VTD spec, stage-1 page table could support 4-level and > 5-level paging. > > However, 5-level paging translation emulation is unsupported yet. > That means the only supported value for aw_bits is 48. So default > aw_bits to 48

[PATCH v5 16/20] intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2

2024-11-11 Thread Zhenzhong Duan
According to VTD spec, stage-1 page table could support 4-level and 5-level paging. However, 5-level paging translation emulation is unsupported yet. That means the only supported value for aw_bits is 48. So default aw_bits to 48 in scalable modern mode. For legacy and scalable legacy modes, 48 i