Re: [PATCH v5 12/22] target/arm: generate xml description of our SVE registers

On 1/14/20 5:09 AM, Alex Bennée wrote: > We also expose a the helpers to read/write the the registers. > > Signed-off-by: Alex Bennée > > --- > v2 > - instead of zNpM expose zN at sve_max_vq width > - wrap union in union q(us), d(usf), s(usf), h(usf), b(us) > v3 > - add a vg pseudo registe

[PATCH v5 12/22] target/arm: generate xml description of our SVE registers

We also expose a the helpers to read/write the the registers. Signed-off-by: Alex Bennée --- v2 - instead of zNpM expose zN at sve_max_vq width - wrap union in union q(us), d(usf), s(usf), h(usf), b(us) v3 - add a vg pseudo register for current width - spacing fixes - use switch/case f