On Sat, Dec 11, 2021 at 2:26 PM Anup Patel wrote:
>
> The AIA specification adds new CSRs for RV32 so that RISC-V hart can
> support 64 local interrupts on both RV32 and RV64.
>
> Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h| 14 +-
> t
The AIA specification adds new CSRs for RV32 so that RISC-V hart can
support 64 local interrupts on both RV32 and RV64.
Signed-off-by: Anup Patel
---
target/riscv/cpu.h| 14 +-
target/riscv/cpu_helper.c | 10 +-
target/riscv/csr.c| 560 +++---
ta
