Re: [PATCH v5 02/12] tcg/riscv: Add basic support for vector

On 10/6/24 19:56, LIU Zhiwei wrote: +} tcg_target_call_clobber_regs = -1u; tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); I believe all of the vector registers are call-clobbered? This needs - tcg_target_call_clobber_regs = -1u; + tcg_target_cal

Re: [PATCH v5 02/12] tcg/riscv: Add basic support for vector

On 10/6/24 19:56, LIU Zhiwei wrote: @@ -2100,6 +2136,30 @@ static void tcg_target_init(TCGContext *s) { tcg_target_available_regs[TCG_TYPE_I32] = 0x; tcg_target_available_regs[TCG_TYPE_I64] = 0x; +s->reserved_regs = 0; + +switch (riscv_lg2_vlenb) { +case

[PATCH v5 02/12] tcg/riscv: Add basic support for vector

From: Huang Shiyuan The RISC-V vector instruction set utilizes the LMUL field to group multiple registers, enabling variable-length vector registers. This implementation uses only the first register number of each group while reserving the other register numbers within the group. In TCG, each VE