Re: [PATCH v5 01/11] hw/misc: Add NPCM7xx System Global Control Registers device model

2020-07-11 Thread Havard Skinnemoen
On Fri, Jul 10, 2020 at 11:46 PM Havard Skinnemoen wrote: > > On Fri, Jul 10, 2020 at 2:31 AM Philippe Mathieu-Daudé > wrote: > > > > On 7/9/20 7:42 PM, Havard Skinnemoen wrote: > > > On Thu, Jul 9, 2020 at 10:24 AM Philippe Mathieu-Daudé > > > wrote: > > >> On 7/9/20 7:09 PM, Havard Skinnemoe

Re: [PATCH v5 01/11] hw/misc: Add NPCM7xx System Global Control Registers device model

2020-07-10 Thread Havard Skinnemoen
On Fri, Jul 10, 2020 at 2:31 AM Philippe Mathieu-Daudé wrote: > > On 7/9/20 7:42 PM, Havard Skinnemoen wrote: > > On Thu, Jul 9, 2020 at 10:24 AM Philippe Mathieu-Daudé > > wrote: > >> On 7/9/20 7:09 PM, Havard Skinnemoen wrote: > >>> On Thu, Jul 9, 2020 at 9:23 AM Philippe Mathieu-Daudé > >>>

Re: [PATCH v5 01/11] hw/misc: Add NPCM7xx System Global Control Registers device model

2020-07-10 Thread Philippe Mathieu-Daudé
On 7/9/20 7:42 PM, Havard Skinnemoen wrote: > On Thu, Jul 9, 2020 at 10:24 AM Philippe Mathieu-Daudé > wrote: >> On 7/9/20 7:09 PM, Havard Skinnemoen wrote: >>> On Thu, Jul 9, 2020 at 9:23 AM Philippe Mathieu-Daudé >>> wrote: On 7/9/20 8:43 AM, Havard Skinnemoen wrote: > On Wed, Jul 8,

Re: [PATCH v5 01/11] hw/misc: Add NPCM7xx System Global Control Registers device model

2020-07-09 Thread Havard Skinnemoen
On Thu, Jul 9, 2020 at 10:24 AM Philippe Mathieu-Daudé wrote: > > On 7/9/20 7:09 PM, Havard Skinnemoen wrote: > > On Thu, Jul 9, 2020 at 9:23 AM Philippe Mathieu-Daudé > > wrote: > >> On 7/9/20 8:43 AM, Havard Skinnemoen wrote: > >>> On Wed, Jul 8, 2020 at 11:04 PM Philippe Mathieu-Daudé > >>>

Re: [PATCH v5 01/11] hw/misc: Add NPCM7xx System Global Control Registers device model

2020-07-09 Thread Philippe Mathieu-Daudé
On 7/9/20 7:09 PM, Havard Skinnemoen wrote: > On Thu, Jul 9, 2020 at 9:23 AM Philippe Mathieu-Daudé wrote: >> On 7/9/20 8:43 AM, Havard Skinnemoen wrote: >>> On Wed, Jul 8, 2020 at 11:04 PM Philippe Mathieu-Daudé >>> wrote: On 7/9/20 2:35 AM, Havard Skinnemoen wrote: > Implement a devic

Re: [PATCH v5 01/11] hw/misc: Add NPCM7xx System Global Control Registers device model

2020-07-09 Thread Havard Skinnemoen
On Thu, Jul 9, 2020 at 9:23 AM Philippe Mathieu-Daudé wrote: > > On 7/9/20 8:43 AM, Havard Skinnemoen wrote: > > On Wed, Jul 8, 2020 at 11:04 PM Philippe Mathieu-Daudé > > wrote: > >> On 7/9/20 2:35 AM, Havard Skinnemoen wrote: > >>> Implement a device model for the System Global Control Registe

Re: [PATCH v5 01/11] hw/misc: Add NPCM7xx System Global Control Registers device model

2020-07-09 Thread Philippe Mathieu-Daudé
On 7/9/20 8:43 AM, Havard Skinnemoen wrote: > On Wed, Jul 8, 2020 at 11:04 PM Philippe Mathieu-Daudé > wrote: >> On 7/9/20 2:35 AM, Havard Skinnemoen wrote: >>> Implement a device model for the System Global Control Registers in the >>> NPCM730 and NPCM750 BMC SoCs. >>> >>> This is primarily used

Re: [PATCH v5 01/11] hw/misc: Add NPCM7xx System Global Control Registers device model

2020-07-08 Thread Havard Skinnemoen
On Wed, Jul 8, 2020 at 11:04 PM Philippe Mathieu-Daudé wrote: > > On 7/9/20 2:35 AM, Havard Skinnemoen wrote: > > Implement a device model for the System Global Control Registers in the > > NPCM730 and NPCM750 BMC SoCs. > > > > This is primarily used to enable SMP boot (the boot ROM spins reading

Re: [PATCH v5 01/11] hw/misc: Add NPCM7xx System Global Control Registers device model

2020-07-08 Thread Philippe Mathieu-Daudé
On 7/9/20 2:35 AM, Havard Skinnemoen wrote: > Implement a device model for the System Global Control Registers in the > NPCM730 and NPCM750 BMC SoCs. > > This is primarily used to enable SMP boot (the boot ROM spins reading > the SCRPAD register) and DDR memory initialization; other registers are

[PATCH v5 01/11] hw/misc: Add NPCM7xx System Global Control Registers device model

2020-07-08 Thread Havard Skinnemoen
Implement a device model for the System Global Control Registers in the NPCM730 and NPCM750 BMC SoCs. This is primarily used to enable SMP boot (the boot ROM spins reading the SCRPAD register) and DDR memory initialization; other registers are best effort for now. The reset values of the MDLR and