On 2020/2/29 2:46, Richard Henderson wrote:
On 2/28/20 1:19 AM, LIU Zhiwei wrote:
+#define GEN_VEXT_AMO_NOATOMIC_OP(NAME, ETYPE, MTYPE, H, DO_OP, SUF) \
+static void vext_##NAME##_noatomic_op(void *vs3, target_ulong addr, \
+ uint32_t wd, uint32_t idx, CPURISCVState *env, uin
On 2/28/20 1:19 AM, LIU Zhiwei wrote:
>>> +#define GEN_VEXT_AMO_NOATOMIC_OP(NAME, ETYPE, MTYPE, H, DO_OP, SUF) \
>>> +static void vext_##NAME##_noatomic_op(void *vs3, target_ulong addr, \
>>> + uint32_t wd, uint32_t idx, CPURISCVState *env, uintptr_t retaddr)\
>>> +{
On 2020/2/28 13:38, Richard Henderson wrote:
On 2/25/20 2:35 AM, LIU Zhiwei wrote:
+if (s->sew < 2) {
+return false;
+}
This could just as easily be in amo_check?
Yes, it can be done in amo_check.
+
+if (tb_cflags(s->base.tb) & CF_PARALLEL) {
+#ifdef CONFIG_ATOMIC64
+
On 2/25/20 2:35 AM, LIU Zhiwei wrote:
> +if (s->sew < 2) {
> +return false;
> +}
This could just as easily be in amo_check?
> +
> +if (tb_cflags(s->base.tb) & CF_PARALLEL) {
> +#ifdef CONFIG_ATOMIC64
> +fn = fns[0][seq][s->sew - 2];
> +#else
> +gen_helper_exit_
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element operations
in the same vector AMO instruction
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h
