Re: [PATCH v4 3/3] target/riscv: Implement the stval/mtval illegal instruction

2021-12-20 Thread Bin Meng
On Mon, Dec 20, 2021 at 2:49 PM Alistair Francis wrote: > > From: Alistair Francis > > The stval and mtval registers can optionally contain the faulting > instruction on an illegal instruction exception. This patch adds support > for setting the stval and mtval registers. > > The RISC-V spec stat

Re: [PATCH v4 3/3] target/riscv: Implement the stval/mtval illegal instruction

2021-12-20 Thread Richard Henderson
On 12/19/21 10:49 PM, Alistair Francis wrote: From: Alistair Francis The stval and mtval registers can optionally contain the faulting instruction on an illegal instruction exception. This patch adds support for setting the stval and mtval registers. The RISC-V spec states that "The stval regis

[PATCH v4 3/3] target/riscv: Implement the stval/mtval illegal instruction

2021-12-20 Thread Alistair Francis
From: Alistair Francis The stval and mtval registers can optionally contain the faulting instruction on an illegal instruction exception. This patch adds support for setting the stval and mtval registers. The RISC-V spec states that "The stval register can optionally also be used to return the f