Hi Jonathan,
Thanks for the feedbacks.
>-Original Message-
>From: Jonathan Cameron
>Sent: 19 February 2024 16:59
>To: Shiju Jose
>Cc: qemu-devel@nongnu.org; linux-...@vger.kernel.org; tanxiaofei
>; Zengtao (B) ; Linuxarm
>
>Subject: Re: [PATCH v4 3/3] hw/cx
On Mon, 19 Feb 2024 23:00:25 +0800
wrote:
> From: Shiju Jose
>
> CXL spec 3.1 section 8.2.9.9.11.2 describes the DDR5 Error Check Scrub (ECS)
> control feature.
>
> The Error Check Scrub (ECS) is a feature defined in JEDEC DDR5 SDRAM
> Specification (JESD79-5) and allows the DRAM to internally
From: Shiju Jose
CXL spec 3.1 section 8.2.9.9.11.2 describes the DDR5 Error Check Scrub (ECS)
control feature.
The Error Check Scrub (ECS) is a feature defined in JEDEC DDR5 SDRAM
Specification (JESD79-5) and allows the DRAM to internally read, correct
single-bit errors, and write back corrected
