On 2/28/20 11:03 AM, Peter Maydell wrote:
> It occurs to me that we should check what the required
> semantics are for the opposite half of the register
> if the guest writes to one half of it via hcr_writehigh()
> or hcr_writelow() -- is the un-accessed half supposed
> to stay exactly as it is, or
On Fri, 28 Feb 2020 at 18:55, Richard Henderson
wrote:
>
> On 2/28/20 9:34 AM, Peter Maydell wrote:
> > You could refine the valid mask as the & of the bits which we
> > do want to exist in aarch32, rather than &~ of the reserved bits:
> >
> > valid_mask &= TTLBIS | TOCU | TICAB | ...
> >
> > ?
>
On 2/28/20 9:34 AM, Peter Maydell wrote:
> One of us is miscounting, and I don't *think* it's me...
>
> bits 63..0: ff80ff8c9000
> bits 63..32: ff80ff8c
> bits 64..48: ff80
>
> bit 48 looks like it's 0 to me.
Oops, yes, it's me.
> You could refine the valid mask as the & of the bits which
On Fri, 28 Feb 2020 at 16:57, Richard Henderson
wrote:
>
> On 2/28/20 8:22 AM, Peter Maydell wrote:
> >> +if (ri->state == ARM_CP_STATE_AA32) {
> >> +/*
> >> + * Writes from aarch32 mode have more RES0 bits.
> >> + * This includes TDZ, RW, E2H, and more.
> >> +
On 2/28/20 8:22 AM, Peter Maydell wrote:
>> +if (ri->state == ARM_CP_STATE_AA32) {
>> +/*
>> + * Writes from aarch32 mode have more RES0 bits.
>> + * This includes TDZ, RW, E2H, and more.
>> + */
>> +valid_mask &= ~0xff80ff8c9000ull;
>> +}
>
> Is
On Tue, 25 Feb 2020 at 18:08, Richard Henderson
wrote:
>
> Don't merely start with v8.0, handle v7VE as well.
> Notice writes from aarch32 mode, and the bits that
> ought not be settable from there.
>
> Suggested-by: Peter Maydell
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper.c |
Don't merely start with v8.0, handle v7VE as well.
Notice writes from aarch32 mode, and the bits that
ought not be settable from there.
Suggested-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
