Re: [PATCH v4 03/12] tcg/riscv: Add vset{i}vli and ld/st vec ops

2024-09-23 Thread Richard Henderson
On 9/23/24 06:46, LIU Zhiwei wrote: On 2024/9/22 12:46, Richard Henderson wrote: On 9/11/24 15:26, LIU Zhiwei wrote: @@ -2129,6 +2389,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)     static void tcg_out_tb_start(TCGContext *s)   { +    s->riscv_cur_type = TCG_TYPE_COUNT;   /* n

Re: [PATCH v4 03/12] tcg/riscv: Add vset{i}vli and ld/st vec ops

2024-09-22 Thread LIU Zhiwei
On 2024/9/22 12:46, Richard Henderson wrote: On 9/11/24 15:26, LIU Zhiwei wrote: @@ -2129,6 +2389,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)     static void tcg_out_tb_start(TCGContext *s)   { +    s->riscv_cur_type = TCG_TYPE_COUNT;   /* nothing to do */   } I recently re

Re: [PATCH v4 03/12] tcg/riscv: Add vset{i}vli and ld/st vec ops

2024-09-21 Thread Richard Henderson
On 9/11/24 15:26, LIU Zhiwei wrote: @@ -2129,6 +2389,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) static void tcg_out_tb_start(TCGContext *s) { +s->riscv_cur_type = TCG_TYPE_COUNT; /* nothing to do */ } I recently realized that the vector config is call-clobbe

Re: [PATCH v4 03/12] tcg/riscv: Add vset{i}vli and ld/st vec ops

2024-09-11 Thread Richard Henderson
On 9/11/24 06:26, LIU Zhiwei wrote: +static bool lmul_check(int lmul, MemOp vsew) +{ +/* + * For a given supported fractional LMUL setting, implementations must + * support SEW settings between SEW_MIN and LMUL * ELEN, inclusive. + * So if ELEN = 64, LMUL = 1/2, then SEW will supp

[PATCH v4 03/12] tcg/riscv: Add vset{i}vli and ld/st vec ops

2024-09-11 Thread LIU Zhiwei
From: TANG Tiancheng In RISC-V, vector operations require initial vtype and vl using the vset{i}vl{i} instruction. This instruction: 1. Sets the vector length (vl) in bytes 2. Configures the vtype register, which includes: SEW (Single Element Width) LMUL (vector register group multip