Re: [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs

On Tue, Nov 2, 2021 at 4:22 PM Bin Meng wrote: > > On Tue, Nov 2, 2021 at 6:24 PM Anup Patel wrote: > > > > On Tue, Nov 2, 2021 at 12:22 PM Bin Meng wrote: > > > > > > On Tue, Oct 26, 2021 at 2:43 PM Anup Patel wrote: > > > > > > > > A hypervsior can optionally take guest external interrupts us

Re: [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs

On Tue, Nov 2, 2021 at 6:24 PM Anup Patel wrote: > > On Tue, Nov 2, 2021 at 12:22 PM Bin Meng wrote: > > > > On Tue, Oct 26, 2021 at 2:43 PM Anup Patel wrote: > > > > > > A hypervsior can optionally take guest external interrupts using > > > > typo: hypervisor > > Okay, I will update. > > > > >

Re: [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs

On Tue, Nov 2, 2021 at 12:22 PM Bin Meng wrote: > > On Tue, Oct 26, 2021 at 2:43 PM Anup Patel wrote: > > > > A hypervsior can optionally take guest external interrupts using > > typo: hypervisor Okay, I will update. > > > SGEIP bit of hip and hie CSRs. > > > > Signed-off-by: Anup Patel > > Re

Re: [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs

On Tue, Oct 26, 2021 at 2:43 PM Anup Patel wrote: > > A hypervsior can optionally take guest external interrupts using typo: hypervisor > SGEIP bit of hip and hie CSRs. > > Signed-off-by: Anup Patel > Reviewed-by: Alistair Francis > --- > target/riscv/cpu.c | 3 ++- > target/riscv/cpu_b

[PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs

A hypervsior can optionally take guest external interrupts using SGEIP bit of hip and hie CSRs. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 ++- target/riscv/cpu_bits.h | 3 +++ target/riscv/csr.c | 18 +++--- 3 files changed, 16 in