Re: [PATCH v4 0/4] QEMU RISC-V ACLINT Support

On Wed, Sep 29, 2021 at 9:52 AM Alistair Francis wrote: > > On Wed, Sep 29, 2021 at 2:09 PM Anup Patel wrote: > > > > On Tue, Aug 31, 2021 at 4:36 PM Anup Patel wrote: > > > > > > The RISC-V Advanced Core Local Interruptor (ACLINT) is an improvement > > > over the SiFive CLINT but also maintains

Re: [PATCH v4 0/4] QEMU RISC-V ACLINT Support

On Wed, Sep 29, 2021 at 2:09 PM Anup Patel wrote: > > On Tue, Aug 31, 2021 at 4:36 PM Anup Patel wrote: > > > > The RISC-V Advanced Core Local Interruptor (ACLINT) is an improvement > > over the SiFive CLINT but also maintains backward compatibility with > > the SiFive CLINT. > > > > Latest RISC-

Re: [PATCH v4 0/4] QEMU RISC-V ACLINT Support

On Tue, Aug 31, 2021 at 4:36 PM Anup Patel wrote: > > The RISC-V Advanced Core Local Interruptor (ACLINT) is an improvement > over the SiFive CLINT but also maintains backward compatibility with > the SiFive CLINT. > > Latest RISC-V ACLINT specification (will be frozen soon) can be found at: > htt

[PATCH v4 0/4] QEMU RISC-V ACLINT Support

The RISC-V Advanced Core Local Interruptor (ACLINT) is an improvement over the SiFive CLINT but also maintains backward compatibility with the SiFive CLINT. Latest RISC-V ACLINT specification (will be frozen soon) can be found at: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc