Re: [PATCH v4] riscv/gdbstub: add V bit to priv reg

2025-01-05 Thread Alistair Francis
On Mon, Dec 16, 2024 at 7:38 AM Yanfeng Liu wrote: > > This adds virtualization mode (V bit) as bit(2) of register `priv` > per RiscV debug spec v1.0.0-rc4. Checked with gdb-multiarch v12.1. > > Note that GDB may display `INVALID` tag for `priv` reg when V bit > is set, this doesn't affect actual

Re: [PATCH v4] riscv/gdbstub: add V bit to priv reg

2025-01-05 Thread Alistair Francis
On Mon, Dec 16, 2024 at 7:38 AM Yanfeng Liu wrote: > > This adds virtualization mode (V bit) as bit(2) of register `priv` > per RiscV debug spec v1.0.0-rc4. Checked with gdb-multiarch v12.1. > > Note that GDB may display `INVALID` tag for `priv` reg when V bit > is set, this doesn't affect actual

Re: [PATCH v4] riscv/gdbstub: add V bit to priv reg

2024-12-16 Thread Mario Fleischmann
On 15.12.2024 22:37, Yanfeng Liu wrote: This adds virtualization mode (V bit) as bit(2) of register `priv` per RiscV debug spec v1.0.0-rc4. Checked with gdb-multiarch v12.1. Note that GDB may display `INVALID` tag for `priv` reg when V bit is set, this doesn't affect actual access to the bit

[PATCH v4] riscv/gdbstub: add V bit to priv reg

2024-12-15 Thread Yanfeng Liu
This adds virtualization mode (V bit) as bit(2) of register `priv` per RiscV debug spec v1.0.0-rc4. Checked with gdb-multiarch v12.1. Note that GDB may display `INVALID` tag for `priv` reg when V bit is set, this doesn't affect actual access to the bit though. Signed-off-by: Yanfeng Liu --- tar