Aleksandar.
enjoy your vacation.
Regards,
Michael Rolnik
On Tue, Dec 3, 2019 at 3:48 AM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Tuesday, December 3, 2019, Aleksandar Markovic <
> aleksandar.m.m...@gmail.com> wrote:
>
>>
>>
>> On Tuesday, December 3, 2019, Aleksandar M
On Tuesday, December 3, 2019, Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Tuesday, December 3, 2019, Aleksandar Markovic <
> aleksandar.m.m...@gmail.com> wrote:
>
>>
>>
>> On Monday, December 2, 2019, Aleksandar Markovic <
>> aleksandar.m.m...@gmail.com> wrote:
>>
>>>
>>>
>>
On Tuesday, December 3, 2019, Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Monday, December 2, 2019, Aleksandar Markovic <
> aleksandar.m.m...@gmail.com> wrote:
>
>>
>>
>> On Monday, December 2, 2019, Michael Rolnik wrote:
>>
>>> how can I get this elf flags from within QEMU
On Monday, December 2, 2019, Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Monday, December 2, 2019, Michael Rolnik wrote:
>
>> how can I get this elf flags from within QEMU?
>>
>>>
>>>
> In one of files from your "machine" patch, you have this snippet:
>
> +bytes_loa
On Monday, December 2, 2019, Michael Rolnik wrote:
> how can I get this elf flags from within QEMU?
>
>>
>>
In one of files from your "machine" patch, you have this snippet:
+bytes_loaded = load_elf(
+filename, NULL, NULL, NULL, NULL, NULL, NULL, 0, EM_NONE, 0,
0);
With this
how can I get this elf flags from within QEMU?
On Mon, Dec 2, 2019 at 4:01 PM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Monday, December 2, 2019, Michael Rolnik wrote:
>
>> No, I don't.
>> but I also can load and execute a binary file which does not have this
>> informat
On Monday, December 2, 2019, Michael Rolnik wrote:
> No, I don't.
> but I also can load and execute a binary file which does not have this
> information.
>
>>
>>
OK. Let's think about that for a while. I currently think you have here an
opportunity to add a really clean interface from the outset
No, I don't.
but I also can load and execute a binary file which does not have this
information.
On Mon, Dec 2, 2019 at 11:59 AM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Monday, December 2, 2019, Aleksandar Markovic <
> aleksandar.m.m...@gmail.com> wrote:
>
>>
>>
>> On S
On Monday, December 2, 2019, Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Saturday, November 30, 2019, Michael Rolnik wrote:
>
>> There is *-cpu *option where you can specify what CPU you want, if this
>> option is not specified avr6 (avr6-avr-cpu) is chosen.
>>
>> *./avr-so
On Saturday, November 30, 2019, Michael Rolnik wrote:
> There is *-cpu *option where you can specify what CPU you want, if this
> option is not specified avr6 (avr6-avr-cpu) is chosen.
>
> *./avr-softmmu/qemu-system-avr -cpu help*
> avr1-avr-cpu
> avr2-avr-cpu
> avr25-avr-cpu
> avr3-avr-cpu
> avr
On Sunday, December 1, 2019, Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
> Renaming devices such hw/char/avr_usart.c -> hw/char/atmel_usart.c
>> (similarly with the macros) would be enough Aleksandar?
>>
>> On Thursday, November 28, 2019, Michael Rolnik wrote:
>
>> I will rename the
>
> Renaming devices such hw/char/avr_usart.c -> hw/char/atmel_usart.c
> (similarly with the macros) would be enough Aleksandar?
>
> On Thursday, November 28, 2019, Michael Rolnik wrote:
> I will rename them.
>
AVR is the name of a microcontroller lineup, and Atmel is the name of the
company tha
There is *-cpu *option where you can specify what CPU you want, if this
option is not specified avr6 (avr6-avr-cpu) is chosen.
*./avr-softmmu/qemu-system-avr -cpu help*
avr1-avr-cpu
avr2-avr-cpu
avr25-avr-cpu
avr3-avr-cpu
avr31-avr-cpu
avr35-avr-cpu
avr4-avr-cpu
avr5-avr-cpu
avr51-avr-cpu
avr6-avr
On Wednesday, November 27, 2019, Michael Rolnik wrote:
> This series of patches adds 8bit AVR cores to QEMU.
> All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully
> tested yet.
> However I was able to execute simple code with functions. e.g fibonacci
> calculation.
> This serie
On Friday, November 29, 2019, Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Thursday, November 28, 2019, Alex Bennée
> wrote:
>
>>
>> Aleksandar Markovic writes:
>>
>> > On Thursday, November 28, 2019, Michael Rolnik
>> wrote:
>> >
>> >> I don't see why you say that the per
On Thursday, November 28, 2019, Alex Bennée wrote:
>
> Aleksandar Markovic writes:
>
> > On Thursday, November 28, 2019, Michael Rolnik
> wrote:
> >
> >> I don't see why you say that the peripherals are inside the chip, there
> is
> >> CPU within target/avr directory and then there are some per
> Sarah,
> do you mind if use the same license I use for my code?
I'm happy to use the same license.
Kind regards,
Sarah Harris
On Thu, 28 Nov 2019 14:28:19 +0200
Michael Rolnik wrote:
> On Wed, Nov 27, 2019 at 11:06 PM Aleksandar Markovic <
> aleksandar.m.m...@gmail.com> wrote:
>
> > On Wed,
On Thursday, November 28, 2019, Philippe Mathieu-Daudé
wrote:
> On 11/28/19 2:46 PM, Michael Rolnik wrote:
>
>> I will rename them.
>>
>
> Please wait comments from Richard before a version respin.
>
>
Everything went well last 10 or so days, Michael and Sarah were responsive,
the code and series
On Thursday, November 28, 2019, Alex Bennée wrote:
>
> Aleksandar Markovic writes:
>
> > On Thursday, November 28, 2019, Michael Rolnik
> wrote:
> >
> >> I don't see why you say that the peripherals are inside the chip, there
> is
> >> CPU within target/avr directory and then there are some per
Aleksandar Markovic writes:
> On Thursday, November 28, 2019, Michael Rolnik wrote:
>
>> I don't see why you say that the peripherals are inside the chip, there is
>> CPU within target/avr directory and then there are some peripherals in hw
>> directory, CPU does not depend on them. what am I
On Thursday, November 28, 2019, Philippe Mathieu-Daudé
wrote:
> On 11/28/19 2:46 PM, Michael Rolnik wrote:
>
>> I will rename them.
>>
>
>>
Renaming alone won't solve anything.
> Please wait comments from Richard before a version respin.
>
> On Thu, Nov 28, 2019 at 3:41 PM Aleksandar Markovic <
On Wednesday, November 27, 2019, Michael Rolnik wrote:
> This series of patches adds 8bit AVR cores to QEMU.
> All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully
> tested yet.
> However I was able to execute simple code with functions. e.g fibonacci
> calculation.
> This serie
On 11/28/19 2:46 PM, Michael Rolnik wrote:
I will rename them.
Please wait comments from Richard before a version respin.
On Thu, Nov 28, 2019 at 3:41 PM Aleksandar Markovic
mailto:aleksandar.m.m...@gmail.com>> wrote:
[...]
If I understand Aleksandar correctly, the naming is incor
I will rename them.
On Thu, Nov 28, 2019 at 3:41 PM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Thursday, November 28, 2019, Philippe Mathieu-Daudé
> wrote:
>
>> On 11/28/19 2:25 PM, Michael Rolnik wrote:
>>
>>> I don't see why you say that the peripherals are inside the c
On Thursday, November 28, 2019, Philippe Mathieu-Daudé
wrote:
> On 11/28/19 2:25 PM, Michael Rolnik wrote:
>
>> I don't see why you say that the peripherals are inside the chip, there
>> is CPU within target/avr directory and then there are some peripherals in
>> hw directory, CPU does not depend
On Thursday, November 28, 2019, Michael Rolnik wrote:
>
>
> On Wed, Nov 27, 2019 at 11:06 PM Aleksandar Markovic <
> aleksandar.m.m...@gmail.com> wrote:
>
>> On Wed, Nov 27, 2019 at 6:53 PM Michael Rolnik wrote:
>> >
>> > This series of patches adds 8bit AVR cores to QEMU.
>> > All instruction,
On Thursday, November 28, 2019, Michael Rolnik wrote:
> I don't see why you say that the peripherals are inside the chip, there is
> CPU within target/avr directory and then there are some peripherals in hw
> directory, CPU does not depend on them. what am I missing?
>
>>
>>
I meant these periphe
On 11/28/19 2:25 PM, Michael Rolnik wrote:
I don't see why you say that the peripherals are inside the chip, there
is CPU within target/avr directory and then there are some
peripherals in hw directory, CPU does not depend on them. what am I missing?
On Thu, Nov 28, 2019 at 3:22 PM Aleksandar
I don't see why you say that the peripherals are inside the chip, there is
CPU within target/avr directory and then there are some peripherals in hw
directory, CPU does not depend on them. what am I missing?
On Thu, Nov 28, 2019 at 3:22 PM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
On Wed, Nov 27, 2019 at 11:06 PM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
> On Wed, Nov 27, 2019 at 6:53 PM Michael Rolnik wrote:
> >
> > This series of patches adds 8bit AVR cores to QEMU.
> > All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully
> tested yet.
>
On Wed, Nov 27, 2019 at 6:53 PM Michael Rolnik wrote:
>
> This series of patches adds 8bit AVR cores to QEMU.
> All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested
> yet.
> However I was able to execute simple code with functions. e.g fibonacci
> calculation.
> This ser
This series of patches adds 8bit AVR cores to QEMU.
All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested
yet.
However I was able to execute simple code with functions. e.g fibonacci
calculation.
This series of patches include a non real, sample board.
No fuses support yet
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