On 2022/11/18 10:51, Richard Henderson wrote:
I don't think any processor will support overlapping, mutual exclusive
extensions. The decode within the processor would be wildly
complicated by that.
While you might be able to get away with returning false in this
particular case right now,
On 11/17/22 17:46, weiwei wrote:
However, to some extent, JVT and FCSR in statenen CSR are used to
enable/disable
Zfinx and Zcmt extensions. When they are disabled, It seems reasonable to look
for
another insn, just like the processor doesn't support them at all.
From the other aspect, is it
On 2022/11/18 04:57, Richard Henderson wrote:
On 11/17/22 03:44, weiwei wrote:
Missing a smstateen_check. Not mentioned in the instruction
description itself, but it is within the State Enable section of JVT.
smstateen_check have been added in REQUIRE_ZCMT.
Oh. I see. That's wrong, I th
On 11/17/22 03:44, weiwei wrote:
Missing a smstateen_check. Not mentioned in the instruction description itself, but it
is within the State Enable section of JVT.
smstateen_check have been added in REQUIRE_ZCMT.
Oh. I see. That's wrong, I think.
Returning false from trans_* means "no matc
On 2022/11/17 17:56, Richard Henderson wrote:
On 11/16/22 23:03, Weiwei Li wrote:
+target_ulong HELPER(cm_jalt)(CPURISCVState *env, target_ulong index,
+ target_ulong next_pc)
+{
+ target_ulong target = next_pc;
+ target_ulong val = 0;
+ int xlen = riscv_cp
On 11/16/22 23:03, Weiwei Li wrote:
+target_ulong HELPER(cm_jalt)(CPURISCVState *env, target_ulong index,
+ target_ulong next_pc)
+{
+target_ulong target = next_pc;
+target_ulong val = 0;
+int xlen = riscv_cpu_xlen(env);
+
+val = env->jvt;
+
+uint8_
Add encode, trans* functions and helper functions support for Zcmt
instrutions
Add support for jvt csr
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.h| 2 +
target/riscv/cpu_bits.h | 7 +++
target/riscv/csr.c
