Re: [PATCH v3 20/20] target/riscv: Enable uxl field write

On 11/11/21 4:18 PM, Frédéric Pétrot wrote: Still missing the update for write_sstatus, which I think is simply an update to sstatus_v1_10_mask.   I take the liberty to jump in as I face the issue of updating that mask in the   128-bit patches: sstatus_v1_10_mask is a target_ulong, and when

Re: [PATCH v3 20/20] target/riscv: Enable uxl field write

On 11/11/2021 12:49, Richard Henderson wrote: On 11/11/21 6:58 AM, LIU Zhiwei wrote: Signed-off-by: LIU Zhiwei ---   target/riscv/csr.c | 5 ++---   1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 8f8f170768..43eaa6c710 100644 --- a/tar

Re: [PATCH v3 20/20] target/riscv: Enable uxl field write

On 11/11/21 6:58 AM, LIU Zhiwei wrote: Signed-off-by: LIU Zhiwei --- target/riscv/csr.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 8f8f170768..43eaa6c710 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -55

[PATCH v3 20/20] target/riscv: Enable uxl field write

Signed-off-by: LIU Zhiwei --- target/riscv/csr.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 8f8f170768..43eaa6c710 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -553,15 +553,14 @@ static RISCVException write