Re: [PATCH v3 2/3] target/riscv/pmp.c: Fix the index offset on RV64

On Wed, Jul 22, 2020 at 12:58 PM Bin Meng wrote: > > Hi Zong, > > On Tue, Jul 21, 2020 at 8:41 PM Zong Li wrote: > > > > On RV64, the reg_index is 2 (pmpcfg2 CSR) after the seventh pmp > > entry, it is not 1 (pmpcfg1 CSR) like RV32. In the original > > implementation, the second parameter of pmp_

Re: [PATCH v3 2/3] target/riscv/pmp.c: Fix the index offset on RV64

Hi Zong, On Tue, Jul 21, 2020 at 8:41 PM Zong Li wrote: > > On RV64, the reg_index is 2 (pmpcfg2 CSR) after the seventh pmp > entry, it is not 1 (pmpcfg1 CSR) like RV32. In the original > implementation, the second parameter of pmp_write_cfg is > "reg_index * sizeof(target_ulong)", and we get the

[PATCH v3 2/3] target/riscv/pmp.c: Fix the index offset on RV64

On RV64, the reg_index is 2 (pmpcfg2 CSR) after the seventh pmp entry, it is not 1 (pmpcfg1 CSR) like RV32. In the original implementation, the second parameter of pmp_write_cfg is "reg_index * sizeof(target_ulong)", and we get the the result which is started from 16 if reg_index is 2, but we expec