Re: [PATCH v3 15/21] target/riscv: support for 128-bit M extension

On 10/19/21 2:48 AM, Frédéric Pétrot wrote: struct CPURISCVState { target_ulong gpr[32]; target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ +target_ulong hlpr[2]; /* scratch registers for 128-bit div/rem helpers */ We have something similar for s390x, but we ma

[PATCH v3 15/21] target/riscv: support for 128-bit M extension

Given the complexity of the implementation of these instructions, we call helpers to produce their behavior. From an implementation standpoint, we ended up by adding two more tcg globals to return the 128-bit result in a wrapper that itself is called by gen_arith. The sub 128-bit insns are now hand