Re: [PATCH v3 14/21] target/riscv: support for 128-bit arithmetic instructions

On 10/19/21 2:48 AM, Frédéric Pétrot wrote: +static bool gen_setcond_i128(TCGv rl, TCGv rh, + TCGv al, TCGv ah, + TCGv bl, TCGv bh, + TCGCond cond) +{ +switch (cond) { +case TCG_COND_EQ: +tcg_gen_s

[PATCH v3 14/21] target/riscv: support for 128-bit arithmetic instructions

Addition of 128-bit adds and subs in their various sizes. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/insn32.decode | 3 + target/riscv/translate.c| 105 --- target/riscv/insn_trans/trans_rvb.c.inc | 20 +-- target/ri