Re: [PATCH v3 1/5] target/riscv: add vector unit stride load and store instructions

Hi, Richard Thanks for your informative comments. I'm addressing these comments. And a little confused in some comments. On 2020/2/12 14:38, Richard Henderson wrote: On 2/9/20 11:42 PM, LIU Zhiwei wrote: +/* + * As simd_desc supports at most 256 bytes, and in this implementation, + * the max vec

Re: [PATCH v3 1/5] target/riscv: add vector unit stride load and store instructions

Hi, Richard Thanks for comments. On 2020/2/12 14:38, Richard Henderson wrote: On 2/9/20 11:42 PM, LIU Zhiwei wrote: +/* + * As simd_desc supports at most 256 bytes, and in this implementation, + * the max vector group length is 2048 bytes. So split it into two parts. + * + * The first part is

Re: [PATCH v3 1/5] target/riscv: add vector unit stride load and store instructions

On 2/9/20 11:42 PM, LIU Zhiwei wrote: > +/* > + * As simd_desc supports at most 256 bytes, and in this implementation, > + * the max vector group length is 2048 bytes. So split it into two parts. > + * > + * The first part is floor(maxsz, 64), encoded in maxsz of simd_desc. > + * The second part is

[PATCH v3 1/5] target/riscv: add vector unit stride load and store instructions

Vector unit-stride operations access elements stored contiguously in memory starting from the base effective address. The Zvlsseg expands some vector load/store segment instructions, which move multiple contiguous fields in memory to and from consecutively numbered vector register Signed-off-by: