On 12/10/20 2:14 PM, Peter Maydell wrote:
> The CCR is a register most of whose bits are banked between security
> states but where BFHFNMIGN is not, and we keep it in the non-secure
> entry of the v7m.ccr[] array. The logic which tries to handle this
> bit fails to implement the "RAZ/WI from Nons
The CCR is a register most of whose bits are banked between security
states but where BFHFNMIGN is not, and we keep it in the non-secure
entry of the v7m.ccr[] array. The logic which tries to handle this
bit fails to implement the "RAZ/WI from Nonsecure if AIRCR.BFHFNMINS
is zero" requirement; cor
