Re: [PATCH v3 04/14] tcg/riscv: Add riscv vset{i}vli support

2024-09-10 Thread LIU Zhiwei
On 2024/9/10 12:34, Richard Henderson wrote: On 9/9/24 19:46, LIU Zhiwei wrote:     lmul = type - riscv_lg2_vlenb;     if (lmul < -3) {     /* Host VLEN >= 1024 bits. */     vlmul = VLMUL_M1; I am not sure if we should use VLMUL_MF8, Perhaps.  See below.     } else if (lmul < 3) {

Re: [PATCH v3 04/14] tcg/riscv: Add riscv vset{i}vli support

2024-09-09 Thread Richard Henderson
On 9/9/24 19:46, LIU Zhiwei wrote:     lmul = type - riscv_lg2_vlenb;     if (lmul < -3) {     /* Host VLEN >= 1024 bits. */     vlmul = VLMUL_M1; I am not sure if we should use VLMUL_MF8, Perhaps. See below.     } else if (lmul < 3) {     /* 1/8 ... 1 ... 8 */     vlmul = l

Re: [PATCH v3 04/14] tcg/riscv: Add riscv vset{i}vli support

2024-09-09 Thread LIU Zhiwei
On 2024/9/5 14:03, Richard Henderson wrote: On 9/4/24 07:27, LIU Zhiwei wrote: From: TANG Tiancheng In RISC-V, vector operations require initial configuration using the vset{i}vl{i} instruction. This instruction:    1. Sets the vector length (vl) in bytes    2. Configures the vtype register

Re: [PATCH v3 04/14] tcg/riscv: Add riscv vset{i}vli support

2024-09-04 Thread Richard Henderson
On 9/4/24 07:27, LIU Zhiwei wrote: From: TANG Tiancheng In RISC-V, vector operations require initial configuration using the vset{i}vl{i} instruction. This instruction: 1. Sets the vector length (vl) in bytes 2. Configures the vtype register, which includes: SEW (Single Element Widt

[PATCH v3 04/14] tcg/riscv: Add riscv vset{i}vli support

2024-09-04 Thread LIU Zhiwei
From: TANG Tiancheng In RISC-V, vector operations require initial configuration using the vset{i}vl{i} instruction. This instruction: 1. Sets the vector length (vl) in bytes 2. Configures the vtype register, which includes: SEW (Single Element Width) LMUL (vector register group multi